Gate-All-Around Transistor

A Switch You Can Count in Atoms

The camera rests on the cut face of one silicon sheet. It is 5 nm thick; silicon’s lattice constant is 0.543 nm, so the sheet is about 9 unit cells, or about 37 layers of atoms, through.

The bright dots come in pairs: columns of silicon atoms seen along <110>, each pair about 0.14 nm apart. The thin amber film above and below is hafnium oxide; beyond it is the metal gate. Electrons flow along this sheet from one end to the other.

Sheet 5 nm ≈ 9 unit cells ≈ 37 atomic layers · a = 0.5431 nm

Tens of Billions on a Chip

Pull back. This piece of a cell is about 0.25 µm long. Around it are rows of cells like it; the rows make blocks, the blocks make a chip, and a few hundred chips are made together on a wafer 300 mm across.

IBM’s 2 nm gate-all-around chip, shown in 2021, could hold up to 50 billion transistors on a chip the size of a fingernail. Samsung was first into production with 3 nm gate-all-around chips, on 30 June 2022.

Wafer 300 mm · up to ~50 billion transistors on a fingernail-sized chip (IBM 2021)

The Gate Lowers a Barrier

The source is crowded with electrons; the drain sits at a positive voltage. Between them, in the silicon, lies a barrier of energy. While the electrons cannot climb it, the switch is off.

Raise the gate voltage and the barrier sinks; the electrons that get over it multiply. The ink line over the section is that barrier, computed live by the page’s model; the blue beads are electrons passing, drawn in proportion to the current.

Electrons’ energies follow Boltzmann’s distribution. At room temperature, each 60 mV or so off the barrier lets at most ten times as many over. That is the limit of the subthreshold swing: 59.5 mV per decade. Real devices are always a little slower.

Subthreshold swing ≥ (kT/q)·ln 10 = 59.5 mV/dec at 300 K

Why Wrap All Four Sides

Three transistors with the same 12 nm gate stand on one bench, each cut through the middle of its gate. The planar transistor’s gate lies on top of the silicon only. The FinFET stands the silicon up as a thin fin, gated on three sides. The gate-all-around transistor lays the silicon down in thin sheets and gates all four.

The drain’s voltage seeps into the channel from the side and helps electrons over the barrier, out of the gate’s hands. How far it reaches is set by a scale length: the more of the channel the gate wraps, and the thinner the silicon, the shorter it is. The gate has to be 5 to 10 times longer than it to switch off cleanly.

In the page’s model, the planar device’s scale length is about 5.6 nm, and a 12 nm gate cannot switch it off at all. The FinFET’s is about 2.8 nm, with a swing of about 77 mV per decade. The nanosheet’s is about 2.4 nm, with about 72 mV per decade, and more than ten times less leakage.

Scale length λ: planar 5.6 nm · fin 2.8 nm · nanosheet 2.4 nm (page model, 12 nm gate)

Cut Open

From the bottom: the silicon substrate and its shallow trench isolation; the channel of three stacked sheets; the high-k oxide and the metal gate around each one; silicon nitride spacers on both sides of the gate; the source and drain crystals grown at either end; the contacts landing on them; and above, the first and second layers of copper.

The stack in front is an n-type transistor, conducting with electrons; the one behind is p-type, conducting with holes. A pair of them is the basic unit of a CMOS circuit. The insulating oxide that fills the space between the wires has been taken out, so the structure can be seen.

Gate pitch 45 nm · gate 12 nm · three sheets, each 5 × 30 nm

Stacked Sheets

Cut across the middle of the gate and the three sheets lie one above another, each wrapped on top, bottom and both sides first in about 1.5 nm of hafnium oxide, then in the metal gate.

Round their edges, the three sheets have about 210 nm of width under the gate’s control, in a footprint 30 nm wide. Current grows with that width, so a stack drives a lot of current from a small area. The sheets can also be drawn wider or narrower, as the circuit needs.

The small white blocks between the sheets’ ends are the inner spacers. They keep the gate apart from the source and drain and cut the capacitance between them; the chapter on making shows how they get there.

Gated width 3 × 2 × (30 + 5) = 210 nm · footprint 30 nm

Build It, Then Hollow It

Floating sheets cannot be made directly. Instead, layers of silicon and silicon–germanium are grown in turn, like a layer cake; the stack is etched into narrow strips; a dummy polysilicon gate is laid across; the ends are cut away, the silicon–germanium is etched back a little from the sides and the gaps filled with inner spacers; then the source and drain crystals are grown.

Next the dummy gate is removed, and an etch that attacks silicon–germanium but not silicon hollows out every silicon–germanium layer, leaving the sheets hanging between source and drain. This is the channel release. Finally a film of hafnium oxide is laid along the gaps and metal fills them, and the gate closes round every sheet.

Stack → strips → dummy gate → cut → inner spacers → source/drain → open → release → high-k → metal gate

“2 nm” Is Not 2 nm

A chip’s “so many nanometres” has long been the name of a generation, not the size of anything on it. In the 2022 International Roadmap for Devices and Systems (IRDS), the generation called “2 nm” has a gate pitch of 45 nm, a tightest metal pitch of 20 nm and a gate length of 14 nm.

This model is built to those sizes: 45 nm between gate centres, a 12 nm gate, sheets 5 nm thick. Nothing on the transistor is 2 nm.

IRDS 2022: “2 nm” = G45M20 (gate pitch 45 nm, metal pitch 20 nm)

What Comes Next

The forksheet puts an insulating wall between the n-type and p-type stacks so they can sit closer. imec’s devices of 2021 had just 17 nm between the two.

The complementary FET (CFET) stacks the n-type transistor on top of the p-type, two transistors in one footprint. In 2023 Intel showed stacked devices at a 60 nm gate pitch and TSMC at 48 nm, both with n-type on top.

Backside power moves the power lines from above the transistors to the back of the substrate, feeding them from below through tiny vias, so the wiring above carries only signals. Intel’s 18A already uses it (PowerVia); TSMC planned volume production of its A16 for 2026, since reported as moving to 2027.

Forksheet · complementary stack (n over p) · backside power

Taken Apart

The layers slide apart vertically: substrate, isolation, source and drain, sheets, hafnium oxide, metal gate, spacers, contacts, two layers of copper. Rest the pointer on one and it is lifted out on its own and named.